HP OpenVMS Systems

6.2.2.2 Built-in Functions Specific to I64 Systems

The <builtins.h> header file contains a section at the top conditionalized to just __ia64 with the support for built-in functions specific to I64 systems. This includes macro definitions for all of the registers that can be specified to the __getReg, __setReg, __getIndReg, and __setIndReg built-in functions. Parameters that are const -qualified require an argument that is a compile-time constant.

The following sections describe the HP C built-in functions available on OpenVMS I64 systems.

6.2.2.3 Get Hardware Register Value ( __getReg)

The __getReg function gets the value from a hardware register based on the register index specified. This function produces a corresponding mov = r instruction.

This function has the following format:

whichReg

The index of the hardware register from which the value is obtained. The __getReg and __setReg functions can access the following registers:

Register Name whichReg _IA64_REG_IP 1016 _IA64_REG_PSR 1019 _IA64_REG_PSR_L 1019 General Integer Registers: Register Name whichReg _IA64_REG_GP 1025 _IA64_REG_SP 1036 _IA64_REG_TP 1037 Application Registers: Register Name whichReg _IA64_REG_AR_KR0 3072 _IA64_REG_AR_KR1 3073 _IA64_REG_AR_KR2 3074 _IA64_REG_AR_KR3 3075 _IA64_REG_AR_KR4 3076 _IA64_REG_AR_KR5 3077 _IA64_REG_AR_KR6 3078 _IA64_REG_AR_KR7 3079 _IA64_REG_AR_RSC 3088 _IA64_REG_AR_BSP 3089 _IA64_REG_AR_BSPSTORE 3090 _IA64_REG_AR_RNAT 3091 _IA64_REG_AR_FCR 3093 _IA64_REG_AR_EFLAG 3096 _IA64_REG_AR_CSD 3097 _IA64_REG_AR_SSD 3098 _IA64_REG_AR_CFLAG 3099 _IA64_REG_AR_FSR 3100 _IA64_REG_AR_FIR 3101 _IA64_REG_AR_FDR 3102 _IA64_REG_AR_CCV 3104 _IA64_REG_AR_UNAT 3108 _IA64_REG_AR_FPSR 3112 _IA64_REG_AR_ITC 3116 _IA64_REG_AR_PFS 3136 _IA64_REG_AR_LC 3137 _IA64_REG_AR_EC 3138 Control Registers: Register Name whichReg _IA64_REG_CR_DCR 4096 _IA64_REG_CR_ITM 4097 _IA64_REG_CR_IVA 4098 _IA64_REG_CR_PTA 4104 _IA64_REG_CR_IPSR 4112 _IA64_REG_CR_ISR 4113 _IA64_REG_CR_IIP 4115 _IA64_REG_CR_IFA 4116 _IA64_REG_CR_ITIR 4117 _IA64_REG_CR_IIPA 4118 _IA64_REG_CR_IFS 4119 _IA64_REG_CR_IIM 4120 _IA64_REG_CR_IHA 4121 _IA64_REG_CR_LID 4160 _IA64_REG_CR_IVR 4161 * _IA64_REG_CR_TPR 4162 _IA64_REG_CR_EOI 4163 _IA64_REG_CR_IRR0 4164 * _IA64_REG_CR_IRR1 4165 * _IA64_REG_CR_IRR2 4166 * _IA64_REG_CR_IRR3 4167 * _IA64_REG_CR_ITV 4168 _IA64_REG_CR_PMV 4169 _IA64_REG_CR_CMCV 4170 _IA64_REG_CR_LRR0 4176 _IA64_REG_CR_LRR1 4177 * getReg only

6.2.2.4 Set Hardware Register Value ( __setReg)

The __setReg function sets the value for a hardware register based on the register index specified. This function produces a corresponding mov = r instruction.

This function has the following format:

whichReg

The index of the hardware register whose value is being set. See the __getReg functions for the list of registers that can be accessed.

value

The value to which the register is set.

6.2.2.5 Get Index Register Value ( __getIndReg)

The __getIndReg function returns the value of an indexed register. The function accesses a register (index) in a register file (whichIndReg) of 64-bit registers.

This function has the following format:

whichIndReg

The register file.

index

The index in the register file of the hardware register whose value is being requested. See the __getReg functions for the list of registers that can be accessed.

Indirect Registers for getIndReg and setIndReg:

Register Name whichReg _IA64_REG_INDR_CPUID 9000 * _IA64_REG_INDR_DBR 9001 _IA64_REG_INDR_IBR 9002 _IA64_REG_INDR_PKR 9003 _IA64_REG_INDR_PMC 9004 _IA64_REG_INDR_PMD 9005 _IA64_REG_INDR_RR 9006 _IA64_REG_INDR_RESERVED 9007 * getIndReg only

6.2.2.6 Set Index Register Value ( __setIndReg)

The __setIndReg function copies a value into an indexed register. The function accesses a register (index) in a register file (whichIndReg) of 64-bit registers.

This function has the following format:

whichIndReg

The register file.

index

The index in the register file of the hardware register to be set. See the __getIndReg function for the list of registers that can be accessed.

value

The value to which the register is set.

6.2.2.7 Generate Break Instruction ( __break)

The __break function generates a break instruction with an immediate.

This function has the following format:

__break_arg

An immediate value for the __break instruction to use.

6.2.2.8 Serialize Data ( __dsrlz)

The __dsrlz function serializes data. Maps to the srlz.d instruction.

This function has the following format:

6.2.2.9 Flush Cache Instruction ( __fc)

The __fc function flushes a cache line associated with the address given by the argument. Maps to the fcr instruction.

This function has the following format:

__address

A 64-bit address, as opposed to a 32-bit or 64-bit pointer, that is loaded into a 64-bit general register used by the instruction to be generated.

6.2.2.10 Flush Write Buffers ( __fwb)

The __fwb function flushes the write buffers. Maps to the fwb instruction.

This function has the following format:

6.2.2.11 Invalidate ALAT ( __invalat)

The __invalat function invalidates ALAT. Maps to the invala instruction.

This function has the following format:

6.2.2.12 Invalidate ALAT ( __invala)

The __invala function is the same as the __invalat function.

6.2.2.13 Execute Serialize ( __isrlz)

The __isrlz function executes the serialize instruction. Maps to the srlz.i instruction.

This function has the following format:

6.2.2.14 Insert Data Address Translation Cache ( __itcd)

The __itcd function inserts an entry into the data translation cache. Maps to the itc.d instruction.

This function has the following format:

pa

A 64-bit address, as opposed to a 32-bit or 64-bit pointer, that is loaded into a 64-bit general register used by the instruction to be generated.

6.2.2.15 Insert Instruction Address Translation Cache ( __itci)

The __itci function inserts an entry into the instruction translation cache. Maps to the itc.i instruction.

This function has the following format:

pa

A 64-bit address, as opposed to a 32-bit or 64-bit pointer, that is loaded into a 64-bit general register used by the instruction to be generated.

6.2.2.16 Insert Data Translation Register ( __itrd)

The __itrd function maps to the itr.d instruction.

This function has the following format:

whichTransReg

The data translation register to be used by the itr.d instruction.

pa

A 64-bit address, as opposed to a 32-bit or 64-bit pointer, that is loaded into a 64-bit general register used by the instruction to be generated.

6.2.2.17 Insert Instruction Translation Register ( __itri)

The __itri function maps to the itr.i instruction.

This function has the following format:

whichTransReg

The data translation register to be used by the itr.i instruction.

pa

A 64-bit address, as opposed to a 32-bit or 64-bit pointer, that is loaded into a 64-bit general register used by the instruction to be generated.

6.2.2.18 Purge Translation Cache Entry ( __ptce)

The __ptce function maps to the ptc.e instruction.

This function has the following format:

va

A 64-bit address, as opposed to a 32-bit or 64-bit pointer, that is loaded into a 64-bit general register used by the instruction to be generated.

6.2.2.19 Purge Global Translation Cache ( __ptcg)

The __ptcg function purges the global translation cache. Maps to the ptc.g r,r instruction.

This function has the following format:

va

A 64-bit address, as opposed to a 32-bit or 64-bit pointer, that is loaded into a 64-bit general register used by the instruction to be generated.

pagesz

The address range of the purge.

6.2.2.20 Purge Local Translation Cache ( __ptcl)

The __ptcl function purges the local translation cache. Maps to the ptc.l r,r instruction.

This function has the following format:

va

A 64-bit address, as opposed to a 32-bit or 64-bit pointer, that is loaded into a 64-bit general register used by the instruction to be generated.

pagesz

The address range of the purge.

6.2.2.21 Purge Global Translation Cache and ALAT ( __ptcga)

The __ptcga function purges the global translation cache and ALAT. Maps to the ptc.ga r,r instruction.

This function has the following format:

va

A 64-bit address, as opposed to a 32-bit or 64-bit pointer, that is loaded into a 64-bit general register used by the instruction to be generated.

pagesz

The address range of the purge.

6.2.2.22 Purge Data Translation Register ( __ptrd)

The __ptrd function purges the data translation register. Maps to the ptr.d r,r instruction.

This function has the following format:

va

A 64-bit address, as opposed to a 32-bit or 64-bit pointer, that is loaded into a 64-bit general register used by the instruction to be generated.

pagesz

The address range of the purge.

6.2.2.23 Purge Instruction Translation Register ( __ptri)

The __ptri function purges the instruction translation register. Maps to the ptr.i r,r instruction.

This function has the following format:

va

A 64-bit address, as opposed to a 32-bit or 64-bit pointer, that is loaded into a 64-bit general register used by the instruction to be generated.

pagesz

The address range of the purge.

6.2.2.24 Reset System Mask ( __rsm)

The __rsm function resets the system mask bits of the PSR. Maps to the rsm imm24 instruction.

This function has the following format:

mask

An integer value inserted into the instruction as a 24-bit immediate value.

6.2.2.25 Reset User Mask ( __rum)

The __rum function resets the user mask.

This function has the following format:

mask

An integer value inserted into the instruction as a 24-bit immediate value.

6.2.2.26 Set System Mask ( __ssm)

The __ssm function sets the system mask.

This function has the following format:

mask

An integer value inserted into the instruction as a 24-bit immediate value.

6.2.2.27 Set User Mask ( __sum)

The __sum function sets the user mask bits of the PSR. Maps to the sum imm24 instruction.

This function has the following format:

mask

An integer value inserted into the instruction as a 24-bit immediate value.

6.2.2.28 Enable Memory Synchronization ( __synci)

The __synci function enables memory synchronization. Maps to the sync.i instruction.

This function has the following format:

6.2.2.29 Translation Hashed Entry Address ( __thash)

The __thash function generates a translation hash entry address. Maps to the thash r = r instruction.

This function has the following format:

__address

A 64-bit address, as opposed to a 32-bit or 64-bit pointer, that is loaded into a 64-bit general register used by the instruction to be generated.

6.2.2.30 Translation Hashed Entry Tag ( __ttag)

The __ttag function generates a translation hash entry tag. Maps to the ttag r=r instruction.

This function has the following format:

__address

A 64-bit address, as opposed to a 32-bit or 64-bit pointer, that is loaded into a 64-bit general register used by the instruction to be generated.

6.2.2.31 Atomic Compare and Exchange ( _InterlockedCompareExchange_acq)

The _InterlockedCompareExchange_acq function atomically compares and exchanges the value specified by the first argument (a 64-bit pointer). This function maps to the cmpxchg4.acq instruction with appropriate setup.

This function has the following format:

The value at *Destination is compared with the value specified by Comparand. If they are equal, Newval is written to *Destination, and Oldval is returned. The exchange will have taken place if the value returned is equal to the Comparand. The following algorithm is used:

ar.ccv = Comparand; 
Oldval = *Destination;         //Atomic 
if (ar.ccv == *Destination)    //Atomic 
    *Destination = Newval;     //Atomic 
return Oldval; 

Those parts of the algorithm that are marked "Atomic" are performed atomically by the cmpxchg4.acq instruction. This instruction has acquire ordering semantics; that is, the memory read/write is made visible prior to all subsequent data memory accesses of the Destination by other processors.

Destination

The value to be compared with Comparand and, if equal, replaced with the value of Newval.

Newval

The new value to replace the value in Destination.

Comparand

The value with which to compare Destination.

6.2.2.32 Atomic Compare and Exchange ( _InterlockedCompareExchange64_acq)

The _InterlockedCompareExchange64_acq function is the same as the _InterlockedCompareExchange_acq function, except that those parts of the algorithm that are marked "Atomic" are performed by the cmpxchg8.acq instruction.

This function has the following format:

6.2.2.33 Atomic Compare and Exchange ( _InterlockedCompareExchange_rel)

This function is the same as the _InterlockedCompareExchange_acq function except that those parts of the algorithm that are marked "Atomic" are performed by the cmpxchg4.rel instruction with release ordering semantics; that is, the memory read/write is made visible after all previous memory accesses of the Destination by other processors.

This function has the following format:

6.2.2.34 Atomic Compare and Exchange ( _InterlockedCompareExchange64_rel)

This function is the same as the _InterlockedCompareExchange_rel function, except that those parts of the algorithm that are marked "Atomic" are performed by the cmpxchg8.rel instruction.

This function has the following format:

6.2.2.35 Conditional Atomic Compare and Exchange Longword (__CMP_SWAP_LONG)

The __CMP_SWAP_LONG function performs a conditional atomic compare and exchange operation on a longword. The longword pointed to by source is read and compared with the longword old_value. If they are equal, the longword new_value is written into the longword pointed to by source. The read and write is performed atomically, with no intervening access to the same memory region.

The function returns 1 if the write occurs, and 0 otherwise.

This function has the following format:

source

The longword value to be compared with old_value.

old_value

The longword value source is compared with.

new_value

The longword value written into source if source and old_value are equal.