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OpenVMS Alpha System Analysis Tools Manual
SHOW SHM_CPP
Displays information about the shared memory common property partitions
(CPPs). The default display shows a single-page summary that includes a
single line for each CPP.
Format
SHOW SHM_CPP [/ QUALIFIERS]
Parameters
None.
Qualifiers
/ADDRESS=n
Displays a detailed page of information about an individual shared
memory CPP given the address of the SHM_CPP structure.
/ALL
Displays a detailed page of information about each shared memory CPP.
/IDENT=n
Displays a detailed page of information about an individual shared
memory CPP.
/PFN [=option]
Displays PFN data in addition to the basic SHM_CPP. The default is all
lists (free, bad, untested), plus the PFN database pages and the
complete range of PFNs in the CPP.
To display only the complete range of PFNs in the CPP, use the keyword
ALL_FRAGMENTS with the /PFN qualifier:
To display only the bad page list, use the keyword BAD with
the /PFN qualifier:
To display only the free page list, use the keyword FREE with
the /PFN qualifier:
To display the PFNs containing the PFN database, use the keyword
PFNDB with the /PFN qualifier:
To display only the untested page list, use the keyword
UNTESTED with the /PFN qualifier:
To display multiple lists, you can combine keywords with the /PFN
qualifier:
If you specify /PFN without /ALL, /IDENT, or /ADDRESS, then the system
displays the PFN lists from the last shared memory CPP accessed.
Examples
| #1 |
SDA> SHOW SHM_CPP
Summary of Shared Memory Common Property Partitions
---------------------------------------------------
Base address of SHM_CPP array: FFFFFFFF.7F2BA140
Maximum number of SHM_CPP entries: 00000007
Size of each SHM_CPP: 00000240
Maximum fragment count per SHM_CPP: 00000010
Valid CPP count: 00000001
ID SHM_CPP address MinPFN MaxPFN Page count Free pages Flags
---- ----------------- -------- -------- -------- -------- --------
-- SHM_CPP IDs 0000 to 0002: VALID flag clear --
0003 FFFFFFFF.7F2BA800 00060000 0007FFFF 00020000 0001FCF7 00000001 VALID
-- SHM_CPP IDs 0004 to 0006: VALID flag clear --
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This example shows the default output for the SHOW SHM_CPP command.
| #2 |
SDA> SHOW SHM_CPP/IDENT=3
Shared Memory CPP 0003
----------------------
SHM_CPP address: FFFFFFFF.7F2BA800
Version: 00000001 Flags: 00000001 VALID
Size: 00000000.000000C0 Page count: 00020000
Actual fragment count: 00000001 Minimum PFN: 00060000
Maximum fragment count: 00000010 Maximum PFN: 0007FFFF
Length of free page list: 0001FCF7
Length of bad page list: 00000000
Length of untested page list: 00000000
PMAP array for PFN database pages
PMAP Start PFN PFN count
----- -------- --------
0. 00060053 00000280
PMAP array for all fragments
PMAP Start PFN PFN count
----- -------- --------
0. 00060000 00020000
GLock address: FFFFFFFF.7F2BA8C0 Handle: 80000000.00010D19
GLock name: SHM_CPP00000003 Flags: 00
Owner count: 00 Owner node: 00
Node sequence: 0000 Owner: 000000
IPL: 08 Previous IPL: 00
Wait bitmask: 00000000.00000000 Timeout: 00249F00
Thread ID: 00000000.00000000
Connected GNode bitmask: FFFFFFFF.7F2BA900
Valid bits: 00000004 State: 00000000.00000000
Unit count: 0001 Unit size: QUADWORD
Unit bitmask:
........ ........ ........ .......7 00000000
Ranges of free pages
Range Start PFN PFN count
----- -------- --------
1. 000602F6 00000002
2. 0006030B 0001FCF5
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This example shows the details for a single SHM_CPP.
SHOW SHM_REG
Displays information about shared memory regions. The default display
shows a single page summary that includes a single line for each region.
Format
SHOW SHM_REG [/ QUALIFIERS] [name]
Parameter
name
Detailed page of information about the named region.
Qualifiers
/ADDRESS=n
Displays a detailed page of information about an individual region
given the address of the SHM_REG structure.
/ALL
Displays a detailed page of information about each region.
/IDENT=n
Displays a detailed page of information about the specified region.
Examples
1. SDA>SHOW SHM_REG
Summary of Shared Memory Regions
--------------------------------
Base address of SHM_REG array: FFFFFFFF.7F2BB140
Maximum number of SHM_REG entries: 00000040
Size of each SHM_REG: 00000208
Base address of SHM_DESC array: FFFFFFFF.7F2DC000
Valid region count: 00000009
ID SHM_REG address Region Tag SysVA / GSTX Flags
---- ----------------- --------------------------------------- ----------------- --------
0000 FFFFFFFF.7F2BB140 SYS$GALAXY_MANAGEMENT_DATABASE FFFFFFFF.7F234000 00000001 VALID
0001 FFFFFFFF.7F2BB348 SYS$SHARED_MEMORY_PFN_DATABASE FFFFFFFE.00000000 00000001 VALID
0002 FFFFFFFF.7F2BB550 SMCI$SECTION_PBA_04001 -<None>- 00000001 VALID
0003 FFFFFFFF.7F2BB758 GLX$CPU$BALANCER$SYSGBL 0000013F 00000005 VALID SHARED_CONTEXT_VALID
0004 FFFFFFFF.7F2BB960 SMCI$CHANNEL_PBA_0_1 FFFFFFFF.8F3AE000 00000001 VALID
0005 FFFFFFFF.7F2BBB68 SMCI$CHANNEL_PBA_0_2 FFFFFFFF.8FAEE000 00000001 VALID
0006 FFFFFFFF.7F2BBD70 SMCI$CHANNEL_PBA_1_2 -<Not Attached>- 00000001 VALID
0007 FFFFFFFF.7F2BBF78 LAN$SHM_REG FFFFFFFF.7F20C000 00000009 VALID ATTACH_DETACH
0008 FFFFFFFF.7F2BC180 GLX$CPU_BAL_GLOCK $000006 00000140 00000005 VALID SHARED_CONTEXT_VALID
-- SHM_REG IDs 0009 to 003F: never used --
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This example shows the summary of all shared memory regions in the
system.
2. SDA> SHOW SHM_REG SMCI$CHANNEL_PBA_0_1
--------------------------------------
SHM_REG address: FFFFFFFF.7F2BB960
Version: 00000001 Flags: 00000001 VALID
Index/Sequence: 0004/00000003 Size: 00000000.00000120
Region tag: SMCI$CHANNEL_PBA_0_1
Creation time: 31-MAR-1999 14:11:11.37
SHM_DESC address: FFFFFFFF.7F2DC200
Version: 00000001 Flags: 00000005 ATTACHED SYS_VA_VALID
System VA: FFFFFFFF.8F3AE000 Virtual size: 00000000.00274000
I/O ref count: 00000000.00000000
Index/Sequence: 0004/00000003 Context: FFFFFFFF.80F42480
Callback: FFFFFFFF.8F38E5C0 SYS$PBDRIVER+185C0
MMAP address: FFFFFFFF.7F2BB9E0
Level count: 0001 Flags: 0001 VALID
Top page count: 00000001 Virtual size: 00000000.00274000
PFN list page count: 00000001 First PFN: 000602D4
Data page count: 00000009
GLock address: FFFFFFFF.7F2BBA80 Handle: 80000000.00010F51
GLock name: SHM_REG00000004 Flags: 00
Owner count: 00 Owner node: 00
Node sequence: 0000 Owner: 000000
IPL: 08 Previous IPL: 00
Wait bitmask: 00000000.00000000 Timeout: 002DC6C0
Thread ID: 00000000.00000000
Attached GNode bitmask: FFFFFFFF.7F2BBAC0
Valid bits: 00000004 State: 00000000.00000012 AUTO_LOCK SET_COUNT
Unit count: 0001 Unit size: QUADWORD
Lock IPL: 08 Saved IPL: 00000008
Count of bits set: 00000002
Unit bitmask:
........ ........ ........ .......3 00000000
I/O in progress bitmask: FFFFFFFF.7F2BBAF8
Valid bits: 00000004 State: 00000000.00000012 AUTO_LOCK SET_COUNT
Unit count: 0001 Unit size: QUADWORD
Lock IPL: 08 Saved IPL: 00000000
Count of bits set: 00000000
Unit bitmask:
........ ........ ........ .......0 00000000
SHM_CPP bitmask: FFFFFFFF.7F2BBB30
Valid bits: 00000007 State: 00000000.00000000
Unit count: 0001 Unit size: QUADWORD
Unit bitmask:
........ ........ ........ ......08 00000000)
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This example shows the details for a single shared memory region.
SHOW SPINLOCKS
Displays the multiprocessing synchronization data structures.
Format
SHOW SPINLOCKS
{[name]|/ADDRESS=expression|/INDEX=expression}
[/COUNTS|/OWNED|/DYNAMIC|/STATIC
|/PCB|/PORT|/CACHED_PCB|/MAILBOX]
[{/BRIEF|/FULL}]
Parameter
name
Name of the spinlock to be displayed. Device spinlock names are of the
form node$lock, where node indicates the OpenVMS Cluster node name and
lock indicates the device and controller identification (for example,
HAETAR$DUA). If there is no OpenVMS Cluster node name, the dollar sign
($) is also skipped (for example, DUA). This parameter cannot be used
to identify mailbox, PCB, or cached PCB spinlocks.
Qualifiers
/ADDRESS=expression
Displays the spinlock at the address specified in expression.
You can use the /ADDRESS qualifier to display a specific device
spinlock; however, the name of the spinlock is listed as
"Unknown" in the display.
/BRIEF
Produces a condensed display of the spinlock information displayed by
default by the SHOW SPINLOCKS command, including the following:
address, spinlock name or device name, IPL or device IPL, rank,
ownership depth, and CPU ID of the owner CPU. If the system under
analysis was executing with full-checking multiprocessing enabled
(according to the setting of the MULTIPROCESSING or SYSTEM_CHECK system
parameter), then the number of waiting CPUs and interlock status are
also displayed.
/CACHED_PCB
Displays all PCB-specific spinlocks associated with PCBs of deleted
processes.
/COUNTS
Produces a display of Spin, Wait, and Acquire counts for each spinlock
(only if full-checking multiprocessing is enabled).
/DYNAMIC
Displays information for all dynamic spinlocks in the system (device,
port, mailbox, PCB, and cached PCB spinlocks).
/FULL
Displays full descriptive and diagnostic information for each displayed
spinlock.
/INDEX=expression
Displays the static spinlock whose index is specified in
expression. You can only use the /INDEX qualifier to display a
named static spinlock.
/MAILBOX
Displays all mailbox-specific spinlocks.
/OWNED
Displays information for all spinlocks owned by the SDA current CPU. If
a processor does not own any spinlocks, SDA displays the following
message:
No spinlocks currently owned by CPU xx
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The xx represents the CPU ID of the processor.
/PCB
Displays all PCB-specific spinlocks.
/PORT
Displays all port spinlocks.
/STATIC
Displays information for all static spinlocks in the system.
Description
The SHOW SPINLOCKS command displays status and diagnostic information
about the multiprocessing synchronization structures known as
spinlocks.
A static spinlock is a spinlock whose data structure
is permanently assembled into the system. Static spinlocks are accessed
as indexes into a vector of longword addresses called the
spinlock vector, the address of which is contained in
SMP$AR_SPNLKVEC. Table 4-26 lists the static spinlocks.
A dynamic spinlock is a spinlock that is created based
on the configuration of a particular system. One such dynamic spinlock
is the device lock SYSMAN creates when configuring a particular device.
This device lock synchronizes access to the device's registers and
certain UCB fields. The system creates a dynamic spinlock by allocating
space from nonpaged pool, rather than assembling the lock into the
system as it does in creating a static spinlock. Other types of dynamic
spinlocks are: port spinlocks, mailbox spinlocks, PCB and cached PCB
spinlocks.
See the Writing OpenVMS Alpha Device Drivers in C for a full discussion of the role of spinlocks in
maintaining synchronization of kernel-mode activities in a
multiprocessing environment.
Table 4-26 Static Spinlocks
| Name |
Description |
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QUEUEAST
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Spinlock for queuing ASTs at IPL 6
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FILSYS
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Spinlock on file system structures
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LCKMGR
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Spinlock on all lock manager structures
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IOLOCK8/SCS
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Spinlock for executing a driver fork process at IPL 8
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TX_SYNCH
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Transaction processing spinlock
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TIMER
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Spinlock for adding and deleting timer queue entries and searching the
timer queue
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PORT
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Template structure for dynamic spinlocks for ports with multiple devices
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IO_MISC
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Miscellaneous short-term I/O spinlocks
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MMG
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Spinlock on memory management, PFN database, swapper, modified page
writer, and creation of per-CPU database structures
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SCHED
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Spinlock on some process data structures and the scheduler database.
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IOLOCK9
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Spinlock for executing a driver fork process at IPL 9
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IOLOCK10
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Spinlock for executing a driver fork process at IPL 10
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IOLOCK11
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Spinlock for executing a driver fork process at IPL 11
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MAILBOX
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Spinlock for sending messages to the permanent system (OPCOM, JOBCTL,
and so on) mailboxes
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POOL
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Spinlock on nonpaged pool database
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PERFMON
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Spinlock for I/O performance monitoring
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INVALIDATE
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Spinlock for system space translation buffer (TB) invalidation
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HWCLK
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Spinlock on hardware clock database, including the quadword containing
the due time of the first timer queue entry (EXE$GQ_1ST_TIME) and the
quadword containing the system time (EXE$GQ_SYSTIME)
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MEGA
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Spinlock for serializing access to fork-wait queue
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EMB/MCHECK
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Spinlock for allocating and releasing error-logging buffers and
synchronizing certain machine error handling
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For each spinlock in the system, SHOW SPINLOCKS provides the following
information:
- Name of the spinlock (or device name for the device lock)
- Address of the spinlock data structure (SPL)
- The owning CPU's CPU ID
- IPL at which allocation of the lock is synchronized on a local
processor
- Number of nested acquisitions of the spinlock by the processor
owning the spinlock (Ownership Depth)
- Rank of the spinlock
- Timeout interval for spinlock acquisition (in terms of 10
milliseconds)
- Shared array (shared spinlock context block pointer)
- Number of processors waiting to obtain the spinlock
- Interlock (synchronization mutex used when full-checking
multiprocessing is enabled)
The last two items (CPUs waiting and Interlock) are only displayed if
full-checking multiprocessing is enabled.
SHOW SPINLOCKS/BRIEF produces a condensed display of this same
information, excluding the share array and timeout interval.
SHOW SPINLOCKS/COUNTS displays only the Spin, Wait, and Acquire counts
for each spinlock.
If the system under analysis was executing with full-checking
multiprocessing enabled, SHOW SPINLOCKS/FULL adds to the spinlock
display the Spin, Wait, and Acquire counts and the last sixteen PCs at
which the lock was acquired or released. If applicable, SDA also
displays the PC of the last release of multiple, nested acquisitions of
the lock.
If no spinlock name, address, or index is given, then information is
displayed for all applicable spinlocks.
Examples
| #1 |
SDA> SHOW SPINLOCKS
System static spinlock structures
---------------------------------
EMB Address 810AE300
Owner CPU ID None IPL 0000001F
Ownership Depth FFFFFFFF Rank 00000000
Timeout Interval 000186A0 Share Array 00000000
CPUs Waiting 00000000 Interlock Free
MCHECK Address 810AE300
Owner CPU ID None IPL 0000001F
Ownership Depth FFFFFFFF Rank 00000000
Timeout Interval 000186A0 Share Array 00000000
CPUs Waiting 00000000 Interlock Free
MEGA Address 810AE400
Owner CPU ID None IPL 0000001F
Ownership Depth FFFFFFFF Rank 00000002
Timeout Interval 000186A0 Share Array 00000000
CPUs Waiting 00000000 Interlock Free
HWCLK Address 810AE500
Owner CPU ID None IPL 00000016
Ownership Depth FFFFFFFF Rank 00000004
Timeout Interval 000186A0 Share Array 00000000
CPUs Waiting 00000000 Interlock Free
.
.
.
System dynamic spinlock structures
----------------------------------
QTV14$OPA Address 8103FB00
Owner CPU ID None DIPL 00000015
Ownership Depth FFFFFFFF Rank FFFFFFFF
Timeout Interval 000186A0 Share Array 00000000
CPUs Waiting 00000000 Interlock Free
QTV14$MBA Address 810AE900
Owner CPU ID None IPL 0000000B
Ownership Depth FFFFFFFF Rank 0000000C
Timeout Interval 000186A0 Share Array 00000000
CPUs Waiting 00000000 Interlock Free
QTV14$NLA Address 810AE900
Owner CPU ID None IPL 0000000B
Ownership Depth FFFFFFFF Rank 0000000C
Timeout Interval 000186A0 Share Array 00000000
CPUs Waiting 00000000 Interlock Free
QTV14$PKA Address 814AA100
Owner CPU ID None DIPL 00000015
Ownership Depth FFFFFFFF Rank FFFFFFFF
Timeout Interval 000186A0 Share Array 00000000
CPUs Waiting 00000000 Interlock Free
.
.
.
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This excerpt illustrates the default output of the SHOW SPINLOCKS
command.
| #2 |
SDA> SHOW SPINLOCKS/BRIEF
System static spinlock structures
---------------------------------
Spinlock Owner CPUs
Address Name IPL Rank Depth CPU Waiting Interlock
-------- ------------ ---- -------- -------- -------- -------- ---------
810AE300 EMB 001F 00000000 FFFFFFFF None 00000000 Free
810AE300 MCHECK 001F 00000000 FFFFFFFF None 00000000 Free
810AE400 MEGA 001F 00000002 FFFFFFFF None 00000000 Free
810AE500 HWCLK 0016 00000004 FFFFFFFF None 00000000 Free
810AE600 INVALIDATE 0015 00000006 FFFFFFFF None 00000000 Free
810AE700 PERFMON 000F 00000008 FFFFFFFF None 00000000 Free
810AE800 POOL 000B 0000000A FFFFFFFF None 00000000 Free
810AE900 MAILBOX 000B 0000000C FFFFFFFF None 00000000 Free
810AEA00 IOLOCK11 000B 0000000E FFFFFFFF None 00000000 Free
810AEB00 IOLOCK10 000A 0000000F FFFFFFFF None 00000000 Free
810AEC00 IOLOCK9 0009 00000010 FFFFFFFF None 00000000 Free
810AED00 SCHED 0008 00000012 00000000 00000000 00000001 Free
810AEE00 MMG 0008 00000014 FFFFFFFF None 00000000 Free
810AEF00 IO_MISC 0008 00000016 FFFFFFFF None 00000000 Free
810AF000 PORT 0008 00000017 FFFFFFFF None 00000000 Free
810AF100 TIMER 0008 00000018 00000000 00000000 00000000 Free
810AF200 TX_SYNCH 0008 00000019 FFFFFFFF None 00000000 Free
810AF300 SCS 0008 0000001A FFFFFFFF None 00000000 Free
810AF400 LCKMGR 0008 0000001B FFFFFFFF None 00000000 Free
810AF500 FILSYS 0008 0000001C FFFFFFFF None 00000000 Free
810AF600 QUEUEAST 0006 0000001E FFFFFFFF None 00000000 Free
System dynamic spinlock structures
----------------------------------
Device Owner CPUs
Address Name DIPL Rank Depth CPU Waiting Interlock
-------- ------------ ---- -------- -------- -------- -------- ---------
8103FB00 QTV14$OPA 0015 FFFFFFFF FFFFFFFF None 00000000 Free
810AE900 QTV14$MBA 000B 0000000C FFFFFFFF None 00000000 Free
810AE900 QTV14$NLA 000B 0000000C FFFFFFFF None 00000000 Free
814AA100 QTV14$PKA 0015 FFFFFFFF FFFFFFFF None 00000000 Free
.
.
.
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This excerpt illustrates the condensed form of the display produced in
the first example.
| #3 |
SDA> SHOW SPINLOCKS/FULL SCHED
System static spinlock structures
---------------------------------
SCHED Address 810AED00
Owner CPU ID 00000000 IPL 00000008
Ownership Depth 00000000 Rank 00000012
Timeout Interval 002DC6C0 Share Array 00000000
CPUs Waiting 00000001 Interlock Free
Spins 00000000.0458E8DC Busy waits 00252E8D
Acquires 00000000.01279BE0
Spinlock SPL$C_SCHED was last acquired or released from:
(Most recently) 8004AD00 EXE$SWTIMER_FORK_C+00170
. 8004B1D4 EXE$SWTIMER_FORK_C+00644
. 8004AD00 EXE$SWTIMER_FORK_C+00170
. 8004B1D4 EXE$SWTIMER_FORK_C+00644
. 8004AD00 EXE$SWTIMER_FORK_C+00170
. 8004B1D4 EXE$SWTIMER_FORK_C+00644
. 8004AD00 EXE$SWTIMER_FORK_C+00170
. 8004B1D4 EXE$SWTIMER_FORK_C+00644
. 8004AD00 EXE$SWTIMER_FORK_C+00170
. 80136A2C SCH$INTERRUPT+0070C
. 80117580 SCH$IDLE_C+002A0
. 8004B230 EXE$SWTIMER_FORK_C+006A0
. 8004AFC4 EXE$SWTIMER_FORK_C+00434
. 80117360 SCH$IDLE_C+00080
. 8012E5F4 EXE$HIBER_INT_C+00074
(Least recently) 80132150 EXE$SCHDWK_C+00110
Last release of multiple acquisitions occurred at:
80262A54 EXE$CHECK_VERSION_C+009F4
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This display shows the detailed information on the SCHED spinlock,
including the PC history.
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