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HP OpenVMS Systems Documentation |
HP OpenVMS Calling Standard
3.9.1.2 Stack Reserve RegionIn some cases, it is desirable to maintain a stack reserve region, which is a minimum-sized region that is immediately above a thread's guard region. A reserve region may be desirable to ensure that exceptions or asynchronous system faults (ASTs) have stack space to execute on a thread's stack, or to ensure that the exception dispatcher and any exception handler that it might call have stack space to execute after detection of an invalid attempt to extend the stack.
This standard does not require a reserve region.
Because accessible memory may be available at addresses lower than those occupied by the guard region, compilers must generate code that never extends the stack past the guard pages into accessible memory that is not allocated to the thread's stack. A general strategy is to access each page of memory down to and possibly including the page corresponding to the intended new value for the SP. If the stack is to be extended by an amount larger than the size of a memory page, then a series of accesses is required that works from higher to lower addressed pages. If any access results in a memory access violation, then the code has made an invalid attempt to extend the stack of the current thread.
This standard defines two methods for stack limit checking: implicit and explicit. The following are two mutually exclusive strategies for implicit stack limit checking:
The stack frame format (see Section 3.4.3) and entry code rules (see Section 3.6.5) generally do not ensure access to the lowest address of a new stack region without introducing an extra access solely for that purpose. Consequently, this standard uses the second strategy. While the amount of implicit stack extension that can be achieved is smaller, the check is achieved at no additional cost. This standard requires that the minimum guard region size is 8192 bytes, the size of the smallest memory protection granularity allowed by the Alpha architecture. If the stack is being extended by an amount less than or equal to 4096 and a reserve region is not required, then explicit stack limit checking is not required. However, because asynchronous interrupts and calls to other procedures may also cause stack extension without explicit stack limit checking, stack extension with implicit limit checking must adhere to a strict set of conventions as follows:
These conventions ensure that the stack pointer is not decremented so that it points to accessible storage beyond the stack limit without this error being detected (either by the guard region being accessed by the thread or by an explicit stack limit check failure). As a matter of practice, the system can provide multiple guard pages in the guard region. When a stack overflow is detected as a result of access to the guard region, one or more guard pages can be unprotected for use by the exception-handling facility, and one or more guard pages can remain protected to provide implicit stack limit checking during exception processing. However, the size of the guard region and the number of guard pages is system defined and is not defined by this standard. If the stack is being extended by an amount of unknown size or by a known size greater than the maximum implicit check size (4096), then a code sequence that follows the rules for implicit stack limit checking can be executed in a loop to access the new stack region incrementally in segments lesser than or equal to the minimum page size (8192 bytes). At least one access must occur in each such segment. The first access must occur between SP and SP - 4096 because, in the absence of more specific information, the previous guaranteed access relative to the current stack pointer may be as much as 4096 bytes greater than the current stack pointer address. The last access must be within 4096 bytes of the intended new value of the stack pointer. These accesses must occur in order, starting with the highest addressed segment and working toward the lowest addressed segment. A more optimal strategy is:
The stack must not be extended incrementally in procedure prologues. A procedure prologue that needs to extend the stack by an amount of unknown size or known size greater than the minimum implicit check size must test new stack segments as just described in a loop that does not modify SP, and then update the stack with one instruction that copies the new stack pointer value into the SP.
The size of the reserve region must be included in the increment size
used for stack limit checks, after which it is not included in the
amount by which the stack is actually extended. (Depending on the size
of the reserve region, this may partially or even completely eliminate
the ability to use implicit stack limit checking.)
If a stack overflow is detected, one of the following results:
Note that if a transparent stack extension is performed, a stack overflow that occurs in a called procedure might cause the stack to be extended. Therefore, the TEB stack limit value must be considered volatile and potentially modified by external procedure calls and by handling of exceptions.
Chapter 4
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Register | Class | Usage |
---|---|---|
R0 | Constant | Always 0. |
R1 | Special |
Global data pointer (GP). Designated to hold the address of the
currently addressable global data segment. Its use is subject to the
following conventions:
The effect of these rules is that GP must be treated as a scratch register at a point of call (that is, it must be saved by the caller), and it must be preserved from entry to exit. |
R2 | Volatile | May not be used to pass information between procedures, either as inputs or outputs. See also Section 4.1.9. |
R3 | Scratch | May be used within and between procedures in any mutually consistent combination of ways under explicit user control. See also Section 4.1.9. |
R4-R7 | Preserved |
General-purpose preserved registers. Used for any value that needs to
be preserved across a procedure call.
May be used within and between procedures in any mutually consistent combination of ways under explicit user control. See also Section 4.1.9. |
R8-R9 | Scratch | Return Value. Can also be used as input (whether or not the procedure has a return value), but not in any additional ways. In addition, R9 is the preferred and recommended register to use when passing the environment value when calling a bound procedure. (See Section 4.7.7 and Section 5.1.2.) |
R10-R11 | Scratch | May be used within and between procedures in any mutually consistent combination of ways under explicit user control. See also Section 4.1.9. |
R12 | Special | Memory stack pointer (SP). Holds the lowest address of the current stack frame. At a call, the stack pointer must point to a 0 mod 16 aligned area. The stack pointer is also used to access any memory arguments upon entry to a function. Except in the case of dynamic stack allocation, code can use the stack pointer to reference stack items without having to set up a frame pointer for this purpose. |
R13 | Special | Reserved as a thread pointer (TP). |
R14-R18 | Volatile | May not be used to pass information between procedures, either as inputs or outputs. See also Section 4.1.9. |
R19-R24 | Scratch | May be used within and between procedures in any mutually consistent combination of ways under explicit user control. See also Section 4.1.9. |
R25 | Special | Argument information (see Section 4.7.5.3). |
R26-R31 | Scratch | May be used within and between procedures in any mutually consistent combination of ways under explicit user control. See also Section 4.1.9. |
IN0-IN7 | Automatic | Stacked input registers. Code may allocate a register stack frame of up to 96 registers with the ALLOC instruction, and partition this frame into three regions: input registers (IN0, IN1, ...), local registers (LOC0, LOC1, ...), and output registers (OUT0, OUT1, ...). R32--R39 (IN0--IN7) are used as incoming argument registers. Arguments beyond these registers appear in memory, as explained in Section 4.7.4. |
LOC0-LOC95 | Automatic | Stacked local registers. Code may allocate a register stack frame of up to 96 registers with the ALLOC instruction, and partition this frame into three regions: input registers (IN0, IN1, ...), local registers (LOC0, LOC1, ...), and output registers (OUT0, OUT1, ...). LOC0-LOC95 are used for local storage. See Section 4.7.4 for more information. |
OUT0-OUT7 | Scratch | Stacked output registers. Code may allocate a register stack frame of up to 8 registers with the ALLOC instruction, and partition this frame into three regions: input registers (IN0, IN1, ...), local registers (LOC0, LOC1, ...), and output registers (OUT0, OUT1, ...). OUT0-OUT7 are used to pass the first eight arguments in calls. See Section 4.7.4 for more information. |
4.1.3 I64 Floating-Point Register Usage
This standard defines the usage of the OpenVMS floating-point registers
as listed in Table 4-2. Floating-point registers F0 through F31 are
termed the static floating-point registers.
Floating-point registers F32 through F127 are termed the
rotating floating-point registers.
Register | Class | Usage |
---|---|---|
F0 | Constant | Always 0.0. |
F1 | Constant | Always 1.0. |
F2-F5 | Preserved | Can be used for any value that needs to be preserved across a procedure call. A procedure using one of the preserved floating-point registers must save and restore the caller's original contents without generating a NaT consumption fault. |
F6-F7 | Scratch | May be used within and between procedures in any mutually consistent combination of ways under explicit user control. |
F8-F9 | Scratch | Argument/Return values. See Sections 4.7.4 and 4.7.6 for the OpenVMS specifications for use of these registers. |
F10-F15 | Scratch | Argument values. See Section 4.7.4 for the OpenVMS specifications for use of these registers. |
F16--F31 | Preserved | Can be used for any value that needs to be preserved across a procedure call. A procedure using one of the preserved floating-point registers must save and restore the caller's original contents without generating a NaT consumption fault. |
F32-F127 | Scratch | Rotating registers or scratch registers. |
VAX floating-point data are never loaded or manipulated in the Itanium floating-point registers. However, VAX floating-point values may be converted to IEEE floating-point values, which are then manipulated in the I64 floating-point registers. |
Predicate registers are single-bit-wide registers used for controlling the execution of predicated instructions. Predicate registers P0 through P15 are termed the static predicate registers. Predicate registers P16 through P127 are termed the rotating predicate registers. This standard defines the usage of the OpenVMS predicate registers as listed in Table 4-3.
Register | Class | Usage |
---|---|---|
P0 | Constant | Always 1. |
P1-P5 | Preserved | Can be used for any predicate value that needs to be preserved across a procedure call. A procedure using one of the preserved predicate registers must save and restore the caller's original contents. |
P6-P13 | Scratch | Can be used within a procedure as a scratch register. |
P14-P15 | Volatile | May not be used to pass information between procedures, either as input or output. See also Section 4.1.9. |
P16-P63 | Preserved | Rotating registers. |
Branch registers are used for making indirect branches. This standard defines the usage of the OpenVMS branch registers as listed in Table 4-4.
Register | Class | Usage |
---|---|---|
B0 | Scratch | Contains the return address on entry to a procedure; otherwise a scratch register. |
B1-B5 | Preserved | Can be used for branch target addresses that need to be preserved across a procedure call. |
B6-B7 | Volatile | May not be used to pass information between procedures, either as input or output. See also Section 4.1.9. |
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